1. Field of the Invention
The present invention generally relates to System-on-a-Chip architecture and more particularly to an improved bridge that provides multiple virtual channels for the devices connecting to the bridge to reduce latencies.
2. Description of the Related Art
Conventional component-based System-on-a-Chip (SoC) communication architectures achieve poor performance. This is primarily due to the blocking nature of their on-chip communication structures associated with handshake protocols, interconnecting processors and their peripheral Intellectual Property (IP) blocks, which induces latencies that degrade performances of bus system hierarchies. Existing chipset bridges connect processors running at clock speeds of 500 MHz or more to system memories and to I/O's that operate at much lower speed, typically below 100 MHz. Conventionally, the main memory subsystems (fast DRAM) offer high throughput, but they often require several system clock cycles of latency. To go beyond 100 MHz bus speed, the choice of electrical interfaces has to evolve to lower voltage swings than the Low Voltage Transistor Transistor Logic (LVTTL) used conventionally. Increasing the frequency is very hard, and strictly relying on it is not a practical solution. In a telecommunication application, such as a router or a switch, a lot of data is exchanged between the I/Os sitting on the Peripheral Component Interface (PCI) buses and the memory. Due to the hierarchical approach in conventional systems, the I/Os on secondary buses cannot access the main memory with high efficiency, since they must first gain access to the secondary and then to the primary PCI bus.
Improvements to the CPU's processing power result in requirements for more bandwidth, and real time applications impose low latencies. For example, an Ethernet LAN adapter card for the 10/100 MBps uses a 32-bit PCI bus for data transmission to the host CPU, but gigabit LANs would stress such buses beyond their capabilities. Also, the memory of a PowerPC host bus allows 800 MBps of data transfer. The maximum theoretical bandwidth of a 32-bit PCI at 33 MHz is, 132 MB, and a 64-bit PCI can read 528 MBps, if it is clocked at 66 MHz. Therefore, there is a need to optimize bandwidth utilization of these buses and the invention discussed below addresses theses needs.